Solid state drives (SSDs) based on a flash memory has gradually replaced conventional magnetic disks, and become an important storage medium for advantages such as excellent random access performance, low density, and low power consumption. In recent years, flash memory technologies develop rapidly, and a storage density has developed from a single level cell to a recent multiple level cell, for example, six bits, and a manufacturing technique develops from 65 nanometers to 10 nanometers. With these developments, a storage density of a flash memory increases rapidly, while reliability of a flash memory decreases greatly. An error-correcting code with a stronger error correction capability is needed to correctly encode and decode data.
To resolve the problem of reliability of a flash memory, a low density parity check code (LDPC) error correction mechanism is used in a solution that is currently widely used. LDPC decoding is implemented by using a belief propagation algorithm, and is classified into hard decision decoding and soft decision decoding. The hard decision decoding has high efficiency and needs a short time for reading and decoding, but can decode only data having a low error rate. The soft decision decoding can correctly decode data having a relatively high error rate, but has a relatively long latency in reading and decoding. When an LDPC code is used as a check code, there is a correlation between a read request time and an error rate, and a time needed by a read request for data having a high error rate is relatively long.
Data is written to a flash memory in an incremental step pulse programming (ISPP) manner. To enable a flash cell to reach a predetermined voltage, a manner of gradually increasing a programming voltage is used. A programming step voltage used to write data determines an error rate of data to a great extent. When the programming step voltage is higher, a predetermined voltage value can be reached after a relatively small quantity of iterations. However, when the programming step voltage is higher, programming accuracy is lower, and an error rate is higher. Therefore, when a programming speed is higher, an error rate is higher; and when a programming speed is lower, an error rate is lower.
For storage in a flash memory, a certain amount of electric charge is stored in a flash cell of the flash memory to represent data. As a storage time increases, the electric charge in the flash cell flows out. When a storage time is longer, a larger amount of electricity is leaked, and an error rate is higher. In the prior art, according to a time of storing data in a flash memory, a write operation on the data may be regulated. If data needs to be stored for a long time, a write operation is performed in a form of a slow write. When data is written at a low speed, an error rate is low, it is more likely that the data can be read correctly. If data needs to be stored for a short time, an error rate caused by leakage of electricity is relatively low, and a write operation may be performed in a form of a fast write. In the prior art, when a read operation is performed, hard decision decoding is first used, and if the hard decision decoding fails, soft decision decoding is used.
In the prior art, read and write operations on a flash memory cannot be flexibly and effectively adjusted, and a new technology needs to be developed to resolve the problem.